Technical Field
The present invention relates to the technical field of field programmable gate array (Field Programmable Gate Array, FPGA) chips, and in particular, to a chip power supply method and a chip.
Related Art
For a large-scale high performance FPGA chip, a problem of excessively high power dissipation occurs inevitably, and a huge quantity of heat may cause severe and unrecoverable damages to the chip. An FPGA chip has a large quantity of configuration memories inside, and power dissipation of the configuration memories is an importance heat source of the chip. Supply voltage of the configuration memories is generally provided by one or more low-dropout circuits (hereinafter LDOs). In some design, to reduce power dissipation, the configuration memories may be used in slices, and controlled by using multiple LDOs. For configuration memory array that is not used, power supply thereof is switched off, so that data of the configuration memory is lost. In other design, to reduce power dissipation, supply voltage of the configuration memories is reduced. For configuration memory array purely used for data storage, this is a nice method, which can not only reduce the supply voltage, but also facilitate data writing. However, as the configuration memories in the FPGA chip provide gate voltage to a negative channel metal oxide semiconductor (NMOS) pass transistor of the FPGA logic array, an excessively low voltage may lead to decrease of data transmission performance and rate.
FIG. 1 is a timing diagram of a power supply method according to the prior art. As shown in FIG. 1, the existing LDO power supply method includes an initial mode, a program mode and a user mode. Power is a supply voltage; LDO_PDB is a startup signal of an LDO (when LDO_PDB=0, the LDO is turned off; and when LDO_PDB=1, the LDO is turned on); VC is an output voltage of the LDO; cwrite is a write signal of configuration memory array; and cclk is a clock signal.
In the existing timing described above, during the initial mode, program mode and user mode, a stable output voltage VC of 1.2 V is provided to the configuration memory, so that the configuration memory consumes a relatively large current during the program mode, and data transmission performance and rate are not satisfactory during the user mode.